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FIGURE 17. 8 An illustration of two possible thermal via connections to the thermal spreading plane. The first via is a solid connection, which is recommended. The second via connection is made with a spoke or web connection to the thermal plane. This is not recommended for a thermal via.

Quick Start Guide to Oracle Fusion Development Validate Date Restriction Dropping a Validate Date Restriction component as a child of a date component allows you to define dates that should be regarded as invalid input but, unlike the previously explained feature, will validate immediately on the user leaving the field.

If the PCB uses build up technology and nested vias are possible, nested vias should be used to connect to the thermal plane. If the PCB uses build-up technology but nested vias are not allowed, the shortest possible path between vias should be used to route the thermal energy into the spreading planes.

Figure 17.8 shows the proper way to connect thermal vias to power or ground planes.A web or spoke via connection is not recommended, as either constricts heat flow into the thermal plane. The exit side of the thermal via should have a Cu ring to anchor it to the PCB. Common thermal via dimensions for exposed pad packages are 1.0 to 1.2 mm center-to-center spacing, 0.3 mm drill diameter, with 0.025 mm Cu plating thickness or higher. Through hole thermal vias should be filled with solder, epoxy, or solder mask to avoid wicking solder from the thermal joints or thermal balls that might otherwise create an open or a reliability hazard. The thermal resistance of an individual thermal via can be easily calculated from the via diameter, the via plating thickness, and the via length between the thermal land and thermal plane using Eq. 17.3. via = lvia

2 diametervia diametervia ( 2 * Tplating ) k * * 2 2

(17.3)

dira[output]~~ repeat !OUTA[output] waitcnt(11_364 +cnt)

90 80 Force to Failure (kgf) 70 60 50 40 30 20 10 0

Force to failure (kgf)

80 70 60 50 40 30 20 10 0

To implement this behavior, you need to set the property InvalidDaysOfWeek to sat sun, to mark Saturday and Sunday as invalid days, and use HintInvalidDaysOfWeek and MessageDetailInvalidDaysOfWeek to define the appropriate messages.

63.8 65.4

55.4 50.9

We need to generate this tone for about a quarter second and then go on to the next tone. We can repeat this code for as many tones as we need as shown in the preceding program segment. This code is incorporated into Program 17-2.

D C B A 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0%

Failure Mode Legend: Mode A: within the solder joint on the substrate side Mode B: pad lift on the substrate side Mode C: within the solder joint on the board side Mode D: pad lift on the board side

FIGURE 59.13 Data set comparing the force-to-failure rate of Pb/Sn, Pb/Sn/Cu and Sn/Ag/Cu assemblies for two different surface finishes (ENIG and SOC). The histograms show a comparison of the different failure modes obtained in the bend tests.37 All samples were tested within one day of board assembly. (Reprinted with permission from Kyocera SLC Technologies. / [2005] IEEE.)

Cyclic Bend Testing In addition to monotonic loading conditions, certain repetitive operations could also lead to mechanical failures. A typical example is a PWB used in cell-phone applications. The PWB could be subjected to multiple small deflections each time the cell-phone keypad is pressed.This can cause an incremental deterioration in the mechanical response of the PWB and lead to solder joint interconnect failures in BGAs mounted on the PWB.This sort of failure mechanism is more prevalent in relatively thin PWBs used in cell-phone applications. However, similar failures could also occur if, for example, multiple runs of ICT are performed on PCAs in highend server/network applications. An industry standard test method has been developed by JEDEC to characterize the response of a PCA to cyclic loading conditions (JESD22-B113).38 The layout of the test board as specified in the test method is similar to that for the monotonic four-point bend test. Some data on the cyclic bend response of SnAgCu solder joints can be found in Reference 39.

80 Force to Failure (kgf) 70 60 50 40 30 20 10 0

{{12 Sep 09 Harprit Sandhu Play8Notes.spin Propeller Tool Ver. 1.2.6 17 Program 2 This program plays 8 notes, bare bones. Define the constants we will use. }} CON _CLKMODE=XTAL1 + PLL2X _XINFREQ = 5_000_000 repfactor =500 delayfact =1_000_000 output = 25 PUB Go dira[output]~~ repeat repeat repfactor !OUTA[output] waitcnt(13_636 +cnt) waitcnt(delayfact+cnt) repeat repfactor !OUTA[output] waitcnt(12_170 +cnt) waitcnt(delayfact+cnt) repeat repfactor !OUTA[output] waitcnt(11470 +cnt) waitcnt(delayfact+cnt) repeat repfactor !OUTA[output] waitcnt(10221 +cnt) waitcnt(delayfact+cnt) repeat repfactor !OUTA[output] waitcnt(9104 +cnt) waitcnt(delayfact+cnt)

ENIG + Sn3Ag0.5Cu Force to Failure (kgf)