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FIGURE 59.2 Flowchart of the solder joint thermomechanical reliability qualification process. Experimental data generated in the lab environment is compared with the expected product end-use conditions. If the package tested is identical to that used in the product, the acceleration transforms are used to map the fatigue life in the lab to the fatigue life in the product end-use conditions. If the package tested is similar but not identical to that used in the product, FEA is performed to account numerically for the differences between the tested and actual package before using the acceleration transforms.

Predicted Fatigue Life Number of years the solder joints are predicted to survive in the expected field use conditions.

NOTE This example serves two purposes. First, it outlines the basic feature of a managed bean and how it can be used for UI-specific code. Second, as noted earlier, it shows that in many cases you can achieve the same result without the need to write code in a managed bean. In this example, by setting the Disabled property on the Commission field to #{bindings.JobId.inputValue!="SA_REP"}, you can achieve the same behavior.

device and the actual environment in which a very similar device would be used. The entire process by which the reliability of a device can be assessed is illustrated in Fig. 59.2. Thermal cycle experiments are typically performed in single-chamber ovens. Dual-chamber systems are sometimes employed, but single-chamber equipment tends to dominate the test space. The main drawback of a dual-chamber oven is the lack of control over the thermal loading profile when transferring from one chamber (or thermal zone) to the other. Regardless of whether a single or dual chamber is used, temperature is cycled from a maximum (Tmax) to a minimum (Tmin) value. Temperature is ramped from one temperature extreme to another at a controlled rate, referred to as the ramp rate.Temperature is also held at the maximum and minimum values for a predetermined time known as the dwell time. Table 59.1 lists typical

PUB Go cognew(Cog_LCD, @stack2) DIRA[0..7]~ DIRA[chipSel]~~ 'osc once to set up 3202 DIRA[chipDin]~~ 'data set up to the chip DIRA[chipDout]~ 'data from the chip to the Propeller DIRA[chipClk]~~ 'oscillates to read in data from internals repeat DataRead:=0 'Clear out old data outa[chipSel]~~ 'Chip select has to be high to start off outa[chipSel]~ 'Go low to start process outa[chipClk]~ outa[chipDin]~~ outa[chipClk]~~ outa[chipClk]~ outa[chipDin]~~ outa[chipClk]~~ 'Clock MUST be low to load data 'must start with Din high to set up 3202 'Clock high to read data in 'Low to load 'High single mode 'High to read (continued)

FIGURE 17. 4 A typical four-layer PCB cross section showing a package with an exposed pad soldered to a thermal landing that is in turn connected to the PCB ground plane through thermal vias. The vias are isolated from the power plane for electrical reasons. In this figure, the ground plane would become the thermal spreading plane assuming it was continuous over a large area.

Thermal Planes Cu planes in the PCB can provide very effective heat spreading for the electronic components. The intent is to conduct the heat over as large an area as possible in order to optimize convection and radiation heat loss from the PCB. Figure 17.4 shows a cross-sectional view of a PCB highlighting features that make good thermal planes. These include:

A thermal landing (sometimes called a thermal collection plate) or solder land to gather the heat that the device is shedding Thermal vias to conduct heat from the thermal landing into a buried plane (most often either the power or ground plane) Continuous Cu to spread the heat A possible thermal landing on the bottom side of the PCB where an indirect heat sink might be attached Isolation areas to ensure that the thermal vias don t short all planes in the PCB

Many integrated circuit (IC) packages are optimized to dump power into such thermal planes in the PCB. Figure 17.5 shows images of packages with exposed pads that are intended

FIGURE 17.5 Two package types with exposed thermal slugs on the bottom of the package intended to be soldered to thermal spreading elements on the PCB.

Program 16-3 (continued)