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If the traces are thin, their thermal resistance is increased and the heat will not spread as far For best thermal performance, use the thickest possible Cu foil material with the thickest possible electroplating Unfortunately, the trace thickness is often specified to achieve the best possible etch performance for tight pitch routing, which in turn gives the smallest PCB with the fewest signal layers and lowest cost Within these limits, ensure that Cu traces are as thick as possible Use them to provide direct thermal conduction paths to thermal features such as thermal vias, thermal side rails, or thermal conduction screw holes..

FIGURE 58.22 SEM Backscattering Electron Image of Tested Sample with Solder-On-Pad Surface finish Package/Ball Interface. The image shows the intermetallics formed at the joint/package interface. These intermetallics include a thick layer of Cu6Sn5 and a thinner layer of Cu3Sn. Small voids are seen at the Cu6Sn5 and Cu3Sn interface.24 (Reprinted with premission from IEEE [2005].)

A curve fit of the data by Cheng22et al. reported by Mei et al.24 as a function of void area and aging time for different temperatures is shown in Fig. 58.23. The fit equation from the Cheng et al.22 data is given as24: Q A = Ct 0.5 exp RT (58.1)

1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50

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Aging Time (day)

FIGURE 58.23 Curve fit of data at three different temperatures based on the data generated by Cheng et al.24 The values are based on experimental measurements of void area versus time for different temperatures. (Reprinted with premission from IEEE [2005].)

A = ratio of voided area to the joint interface area t = time in days Q = activation energy T = absolute temperature in K R = gas constant. C = 145590 (day 0.5) Q = 45413 J/mol (0.47eV)

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With this approximate curve fit, extrapolating to end-use conditions can give an estimate of the time it would take for the voiding to reach 50 percent of the interface area For instance, at 50 C nominal operating temperature, it would take 6000 days (165 years) to reach 50 percent of the interface area It is important to note that the mechanisms that control the propensity and pervasiveness of Kirkendall voiding are not clearly known at this time There isn t enough experimental data in the industry at this time to conclusively validate the aforementioned relations The occurrence of Kirkendall voids is not limited to the package/solder joint interface If OSP is used as the PWB surface finish, the same phenomenon is observed to occur on the PWB side.

24 In terms of strain/strain rate strength, un-aged, SOP-based joints have been shown to have as much as twice the strength of ENiG joints More details on comparison tests are outlined in the next chapter There are a number of other surface finishes used in the industry, such as Electroless Nickel Electroless Palladium Immersion Gold (NiPdAu), Immersion Silver, Immersion Gold, Immersion Tin, OSP and Electrolytic Nickel Gold There are reliability and process trade offs with each surface finish That is why it is recommended that strain/strain rate characterization and thermal cycling be performed for each set of surface finish before it is selected for the specific end-use conditions in which it will be used The industry test methods used to evaluate different surface finishes are outlined in detail in the next chapter 583.

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12 Final Electrical Test Architecture During in-circuit testing (ICT), assemblies are subjected to high strains due to the number and distribution of test points applied underneath BGAs Assemblies are also subjected to high strain rates in ICT because the speed of engagement of test points helps reduce the electrical contact resistance between the test probes and probe pads Thus, from an electrical test perspective, high strain rates are desirable during ICT However, there is a strain/strain rate range beyond which the likelihood of solder joint failure increases The actual strains induced in a printed circuit board assembly (PCBA) is a function not only of the number and layout of test points, but also the fixture design, package and PWB warpage, the surface finish used on the package and PWB, and the fixture actuation rate.